The need for higher resolution lithography in VLSI device processing has led to the development of various resist processes for fabricating finer and more densely-packed features on silicon wafers. One of these is the trilevel process which improves resolution but at a considerable cost in process complexity. In the trilevel process a thick organic planarizing layer is coated to level out the device topography. Next, a thin glass film is coated thereon. A thin layer of photoresist, coated over the glass, is used to pattern the glass. The glass layer then acts as a mask for oxygen plasma etching of the planarizing layer. Finally, the pattern is transferred into the silicon device.
Approaches to simplifying the trilevel process are being investigated. In one approach, a single thick layer of a photosensitive polymer is used. The polymer is designed to take up silicon from a vapor-treatment process in an imagewise fashion after the polymer has been exposed. The silylated portions at the top of the polymer layer act as the etch mask for the portions remaining below. Development is entirely a dry process. Such approaches incorporate some of the advantages of the trilayer process, but tend to be sensitive to flare light in the patterning exposure tool. Flare light can cause a silicon-containing scum which impedes etching.
Another approach involves replacing silicon in a glass layer with silicon in the resist itself for use with a planarizing layer in a bilayer process. For example, both positive- and negative-working presilylated resist materials, wherein silicon is formulated as part of the resist composition, are known. The silicon in the resist can form an SiO.sub.2 etch mask upon exposure to an oxygen plasma. However, the amount of silicon required in presilylated resist formulations to achieve good etch resistance (up to approximately 15% by weight) lowers the glass transition temperature of the resist and renders the resist more hydrophobic. This results in poor developability in aqueous developers. For positive-working materials, thermal and dimensional instability during subsequent processing (pattern-transfer and etching steps) can result.
European Patent Application No. 0 136 130 describes a method of making articles using a resist formed by sorption of an inorganic-containing gas into an organic material. The resist is developed by exposure to a plasma that forms a protective compound. Example III therein describes the use of SiCl.sub.4, (CH.sub.3).sub.2 SiCl.sub.2 and SnCl.sub.4 in a single layer system comprising a negative-working resist containing an azide sensitizer.
U.K. Patent Application GB 2154330 A discloses a method of fabricating semiconductor devices wherein silicon is introduced into novolac resin by exposure to an atmosphere of tetrachlorosilane or tetramethylsilane.
There is a growing need for a lithographic method, capable of producing high resolution submicron patterned resist images having excellent etch resistance and thermal and dimensional stability, which is compatible with existing resist materials and processing facilities and affords convenient device processing.